1. Field of the Invention
The invention relates to the field of electronic switch technology and in particular to a switching device with a series arrangement of JFETs (junction field effect transistors).
2. Description of Related Art
Power switches or switching devices for switching at high operating voltages can be realised in power-electronic circuits by way of cascading or serially arranged transistors. Thereby, according to U.S. Pat. No. 6,822,842 or DE 199 26 109 A1, such switching devices are, for example, indicated as a cascode circuit, and are based on the special arrangement of a MOSFET M and at least one JFET J1, illustrated by FIG. 1. The switches are arranged between a first terminal 1 and a second terminal 2 and are controlled by a control connection 3 of the MOSFET M. This known switching device for high operating voltages based on the cascode topology envisages the connection of several JFETs J2 . . . Jn in series, and thus the attainment of a high blocking voltage. A circuit network 4 is connected between the first terminal 1 and the second terminal 2, for the passive control of the dynamic blocking voltage distribution of the power switch constructed with the transistors arranged in series, wherein avalanche diodes DAv,1-DAV,n of the circuit network 4 are connected between the gate terminals of the JFETs. The manner of functioning of the circuit network 4 for the symmetrical blocking voltage distribution of the JFETs is described in the publication “Balancing Circuit for a 5 kV/50 ns Pulsed Power Switch Based on SiC-JFET Super Cascode” (J. Biela, D. Aggeler, J. W. Kolar, Proceedings of the 17th IEEE Pulsed Power Conference (PPCV'09)).
In the switched-on condition, a voltage drop across each element arises due to the forward resistances of the individual semiconductor switches M, J1 . . . Jn in the series arrangement. Thereby, the sum of all voltage drops particularly with the uppermost JFET Jn of FIG. 1 causes a different gate-source voltage than at the lower JFETs. This different gate-source voltage can lead to the uppermost transistor switching off and thereby becoming high-impedance and experiencing a high forward voltage in the switched-on state, which leads to its destruction in the worst case.